This invention generally relates to electronic systems and in particular it relates to bias generators for self biased phase locked loops.
A Maneatis self-biased phase locked loop (PLL) architecture is based on the prior art self-biasing techniques shown in FIG. 1. The circuit of FIG. 1 includes amplifier A1; PMOS transistors MP1, MP2, MP3, and MP4; NMOS transistors MN1, MN2, MN3, and MN4; and source voltages VDD and VSS. It is very challenging to maintain the stability of this prior art bias generator over process, temperature, and supply variation. Instability in the bias generator will result in clock jitter. Conventionally, feedback-compensation using a resistor and capacitor is used to improve the stability. However, these components sometimes occupy significant silicon area and increase cost.
The bias generator shown in FIG. 1 generates the signals at nodes VCP and VCN, which are used to bias a prior art voltage controlled oscillator (VCO) delay buffer cell shown in FIG. 2. The circuit of FIG. 2 includes PMOS transistors MP5, MP6, MP7, and MP8; NMOS transistors MN5, MN6, and MN7; input nodes VINxe2x88x92 and VIN+; and output nodes VO+ and VOxe2x88x92. The bias generator uses a half-buffer replica and a differential amplifier A1 to keep the current through the VCO delay cell constant, by forcing the voltage at node VCP equal to control voltage VCTRL. The amplifier A1 adjusts the voltage at node VCP to reject supply and substrate voltage noises.
One of the challenges involved in the design of the bias. generator is to maintain stability for applications requiring the VCO to function over a wide frequency range. A block diagram of the bias generator is shown in FIG. 3. H3(S), H2(S) and A(S) represent transfer functions associated respectively with transistors MN3 and MP2 and the amplifier A1. The circuit has two main poles and a zero:             P      1        =          -              1                  ClR          o                      ,            P      2        =                            -                                                    gm                4                            +                              gds                3                            +                              gds                4                                                    Cl              2                                      ⁢                  xe2x80x83                ⁢        and        ⁢                  xe2x80x83                ⁢                  Z          1                    =                                                  Gm              .                              gm                2                                      ⁢                          xe2x80x83                        ⁢                          R              o                                -                      gm            3                                                gm            3                    ⁢                      xe2x80x83                    ⁢                      ClR            o                              
where Gm represents the transconductance of the input transistor of amplifier A1, gm4 represents the transconductance of transistor MN4, gm2 represents the transconductance of transistor MN2, gm3 represents the transconductance of transistor MN3, gds3 represents the conductance of transistor MN3 and gds4 represents the conductance of transistor MN4. P1 and P2 are the two main poles, and Z1 is the zero. Cl and Cl2 represent the load on nodes VCN and VFB respectively and Ro is the output resistance of amplifier A1.
For applications operating over a wide frequency range, and thus a wide control voltage VCTRL range, the location of the poles and zero are always changing, making stability a concern. For example, there is a possibility that the zero, which is in the right half plane, will move to the left half plane for Gmgm2Ro less than  less than gm3. Furthermore, for gm3=Gm, and assuming gm4 greater than  greater than (gds4+gds3), the poles and zero locations become:             P      1        =          -              1                  ClR          o                      ,            P      2        =                            -                                    gm              4                                      Cl              2                                      ⁢                  xe2x80x83                ⁢        and        ⁢                  xe2x80x83                ⁢                  Z          1                    =                        gm          2                Cl            
The new poles and zero locations indicate the presence of a doublet that may deteriorate the time response.
One of the prior art solutions is RC compensation, but this does not eliminate the pole-zero doublet. Also, RC compensation may work well for a given control voltage but with different control voltage VCTRL, the transconductance of transistor MN2 varies making RC compensation difficult to realize for a wide range of control voltages.
A bias generator circuit with improved phase margin without RC compensation includes: a first transistor; a second transistor coupled in parallel with the first transistor; an amplifier having a first input coupled to the first transistor and to a gate of the second transistor, and a second input coupled to a control voltage node; a third transistor coupled in series with the first transistor; a fourth transistor coupled in series with the third transistor and having a gate coupled to an output of the amplifier; a fifth transistor; a sixth transistor coupled in parallel with the fifth transistor; a seventh transistor coupled in series with the fifth transistor; and an eighth transistor coupled in series with the seventh transistor and having a gate coupled to a gate of the fourth transistor. In order to maintain the bias generator stability for. different biasing conditions, the feed-forward path is removed by diode connecting the second transistor instead of connecting the gate of the second transistor to the control voltage node.